The present invention relates generally to semiconductor processing, and more specifically to a method for making insulated gate transistors, including insulated gate field effect transistors (IGFETs) and insulated gate bipolar transistors (IGBTs).
The prior art will be described in terms of fabricating an n-channel enhancement mode power IGFET. IGFETs are often referred to as MOSFETs (metal-oxide-semiconductor field effect transistors), even though most modern IGFETs have polysilicon rather than metal gates. Further, the initial discussion will be limited to embodiments where the transistor comprises a large number of microscopically small cells, each defining a microscopic active device.
The device is fabricated by diffusing impurities into selected regions of an n- epitaxial (epi) layer formed on an n+ substrate. A typical cell comprises a p/p+ body (sometimes referred to as the p-well) formed in the epi layer and an n+ source region formed within the perimeter of the body. The body is p-type over most of its lateral extent but one or more central regions are doped p+. The portion of the body adjacent the surface and between the source region and the n- epi layer defines a channel region.
A polysilicon layer overlies the channel region of each cell and the regions between cells, and is separated from the epi surface by a thin layer of gate oxide. The polysilicon layer forms a common gate electrode for all the cells in the device. Portions of a top metal layer connect the source regions to a common source node while other portions of the top metal layer connect the polysilicon layer to a common gate node. A metal layer is formed on the bottom surface to form a common drain node.
Known technologies for fabricating insulated gate transistors entail multiple diffusions of impurities to define the active regions of the device. The process most commonly used in the industry is a three-diffusion process wherein the p+ portion of the p-well is diffused, followed by gate oxidation and other oxidation and deposition steps. The second diffusion step is then performed to create the larger p-well area, which is usually self-aligned to the polysilicon gate region. Then, the third diffusion step is performed to create the n+ source region. A two-diffusion manufacturing process is disclosed in U.S. Pat. No. 4,860,072, issued Aug. 22, 1989. In this process, the p-well is formed by two separate deposition steps but a single diffusion step.